As DRAMs increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. A principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three dimensional cell capacitors such as trenched or stacked capacitors. This invention concerns stacked capacitor cell constructions.
With the conventional stacked capacitor, the capacitor is formed immediately above and electrically connected to the active device area of the associated MOS transistor of the memory cell. Typically, only the upper surface of the lower storage polysilicon node of the capacitor is utilized for capacitance. However, some attempts have been made to provide constructions to increase capacitance, whereby the back side of one capacitor terminal is used to store charge. Such is shown by way of example by T. Ema et al. "3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMS", IEDM Tech. Digest, pp. 592, 595, 1988 and S. Inoue et al., "A Spread Stacked Capacitor (SSC) Cell For 64 MBit DRAMs", IEDM Tech. Digest, pp. 31-34, 1989.
One standard prior art technique for forming a stacked "crown" cell capacitor is described with reference to FIGS. 1-4. "Crown" capacitors are characterized by upward spire-like, or fin-like projections, thereby increasing surface area and corresponding capacitance as compared to planar capacitors. FIG. 1 illustrates a semiconductor wafer fragment 10 comprised of a bulk substrate 12, word lines 14, 16, field oxide region 18, and an active area 20 for connection with a capacitor. Wafer 10 also comprises a layer of insulating dielectric 22 through which a desired contact opening 24 has been provided to active area 20. Referring to FIGS. 1 and 2, contact opening 24 has an elliptical or circular shape with walls 26. The vertical lines illustrated in FIG. 1 illustrate shading only for identifying sidewalls 26 and depicting a smooth surface which arcs into the page. Such lines do not indicate texture or other patterning. Sidewalls 26 are typically smooth and straight. The elliptical shape of contact 24 can be produced by depositing a photoresist film over the bulk substrate 10 and transferring the contact 24 pattern by photolithographic means using the proper image mask.
Referring to FIG. 3, a layer 28 of conductive material, such as conductively doped polysilicon, is deposited atop wafer 10 and to within contact opening 24. Layer 28 will provide the storage node poly for formation of one of the capacitor plates.
Referring to FIG. 4, polysilicon layer 28 is first chemical mechanical polished or resist planerization dry etched to be flush with the upper surface of insulating layer 22. Thereafter, insulating layer 22 is etched selectively relative to polysilicon to produce an isolated storage node 30 having the illustrated crown portions projecting upwardly from layer 22. Thereafter, a cell dielectric would be deposited, followed by a cell polysilicon layer to complete the capacitor construction.
It is an object of this invention to enable such and similar stacked capacitor constructions to have increased capacitance.